Jet Process
Corporation

Specialists in Gold Tin Solder and Other Coatings & Other Advanced Thin Films

Microelectronics . Semiconductor Packaging . Optoelectronics & Photonics . Solid State Lighting .
Advanced Sensors . Aerospace . Medical . Communications . MEMS

Jet Vapor Deposition (JVD)
#1 For AuSn Vapor Deposition
Wafer Level Packaging

I. ADVANCED PACKAGING MARKET REQUIREMENTS:

  MINIATURIZATION: Headline for microelectronics packaging market drivers: 

  • thinner wafers (Si and III-V), die and packages
  • more device functionality and reliability, e.g. speed, power, durability
  • smaller, lighter, more fragile, more complex devices; e.g. MEMS based devices
  • smaller feature sizes; smaller, denser, more rugged packages: component integration, 3-D stacking, etc.
  • higher power densities; greater thermal and electrical cycling demands
  • more demanding die handling/processing needs (intra device component alignment, etc.) growing need for user friendly processes
  • higher processing temperatures
  • higher thermal (power) peaks; improved thermal dissipation capability
  • improved process yield
  • lower fabrication cost per device; lower end device cost (incl. test, inventory, logistics)

    • Wafer level packaging (WLP) addresses these market needs.

    Wafer level packaging generally means fabrication on the wafer at “wafer level” of the packaging, interconnect and test functions of an integrated circuit (IC device) prior to wafer dicing instead of the traditional process of packaging each device post wafer dicing.


II. AuSn SOLDERS FOR WLP:

    AuSn solders particularly suited to meet WLP requirements for smaller, reliable advanced   semicon packages, demonstrated advantages have led to broad industry acceptance:

  • high reliability, durability
  • outstanding bond strength, thermal cycling stability/reliability
  • well tested, low creep binary compound
  • melt point 278° eutectic composition – may aid post solder device processing, e.g.: hermetic sealing
  • very good electrical and thermal conductor: suitable for high power, high density devices (RF, opto, III-V)
  • enables flux free die attach
  • broad compatibility with wide range of metal surfaces: Au, Ni, Cu, Pt, Cr, Ti, W, etc., and with variety of substrates: Si, Ge, GaAs, GaN, AlN, SiC, CuW, Al2O3, BeO, etc.
  • ROHS compliant by definition
  • benefits hermetic packaging

    • Use of AuSn solder in WLP for advanced, high reliability products is increasing rapidly.


III. AuSn SOLDER TECHNIQUES:

    Traditional solder manufacturing methods often unsuited to WLP

  • Non-vapor deposition:
    • Preforms: Smaller die sizes may limit use of alternative, non-WLP processes (board level and chip scale) for advanced hi rel apps; e.g., stamped preforms not compatible with smaller parts; small die often cannot be processed post singulation; preforms not generally available in rectangles smaller than 10-20 mils or squares below 10 x 10 mils.
    • Solder Pastes: Use of solder pastes subject to screen printing process, control difficulties, uniformity, quality (e.g., voids), reliability, durability and surface quality issues; reflow usage limited unless flux used, which risks outgassing.
    • Electroplating: ECD AuSn processes difficult to control, creating reliability and process cost issues: e.g., device need for pre ECD pattern metal deposition; plating bath control issues, toxic bath chemicals, production process menu changes, need for photoresist patterning, etc., may limit substrate choice and usefulness for smaller die or higher density packages; plating bath additives can contaminate solder interfaces; ECD frequently incompatible with other needed device layers. These and other issues can greatly decrease ECD reliability, device yields, etc., limiting use in advanced/hi rel apps.

      • Older established solder fabrication techniques often can’t meet current market needs for wafer level AuSn packaging solders.

  • Alternative AuSn Vapor Deposition Techniques:

    - For solder thicknesses 2-20 microns, evaporation and sputtering production issues include composition control/reliability, higher costs (equipment capital cost and COO, cycle times, large/major materials loss, etc.) and low throughput; required vacuum and/or higher temperature processing may limit patterning or other process options.

    - Sputter deposition can trap high energy inert gas atoms in the growing film leading to voids on reflow. 

    - E-beam evaporation can produce uneven materials solder film stoichiometry across a wafer leading to hot spots and related defects.

    Market and JPC customer input suggests that evaporated or sputtered AuSn may be less reliable and/or significantly less cost effective than JVD vapor deposited AuSn (see para. IV. below for comparative JVD advantages).
     


IV.  JVD VAPOR DEPOSITED AuSn FOR WLP:

  • Proven: Well controlled, customer qualified process, Demonstrated AuSn solder film quality; hundreds of apps; chosen by industry leaders
  • Quality:
    • reliable, repeatable, scaleable JVD processes; safe, clean, “green” process
    • dense(~96-98% of bulk) uniform, adherent, void free, low stress film
  • Wafer Level Processing: 2” – 8” wafers (also rectangles, other); Si, GaAs, SiC, GaN, etc. 
  • Low Temperature Process: Deposition temperature @ wafer level: ~60°C
  • Composition Control: ±1%; JVD 80/20 AuSn melts @ 280° (± 1-2°)
  • Thickness/Control: 1-20+ microns, ± 5% thickness uniformity
  • Metal Cluster Deposition: Demonstrated high density (4x4µ @ 8µ pitch) bumps, holes & vias
  • Process Compatibility: Flux free soldering, used with liftoff photoresists, low JVD process temperature aids overall device process temperature budgets
  • Volume Production: Reliable, high throughput, low cost volume production; batch and single wafer mode
  • Unequaled Materials Usage Efficiency: AuSn dep source, wire to wafer: >95%; plus clean, easily recoverable/reusable off wafer overspray
  • Available in Situ Ion Bombardment: for wafer clean/oxide removal, e.g. NiO, or film densification
  • Available in Situ Bond/barrier Layers: e.g. TiPtAu; solder layer caps (flash), e.g., Au, Ag
  • Low Cost per Wafer/Device: volume JVD WLP AuSn solders offer industry leading low cost volume production.

    • JVD AuSn offers proven composition control, wafer to wafer reliability, film quality, reliable solder performance, process integration compatibilities, and lower cost (high dep rate, rapid cycling, materials conversion > 90% reliability/yield).

FOLLOW UP:
Questions on tutorial? 
Jet Process runs JVD AuSn samples cost effectively and with very rapid (~5 day) turnaround. Interested? Please contact sales@jetprocess.com

For additional information, click here for the February 2003 Advanced Packaging magazine article on JVD gold tin solder, and click here for the April 2006 FlipChips.com tutorial on Vapor Jet Deposition of Multi-Metal Films.
 

Jet Process Corporation
57B Dodge Avenue, North Haven, CT 06473
Tel: (203) 985-6000 Fax: (203) 985-6007
e-mail: sales@jetprocess.com